Amps <- & -> Embedded
Measuring the soft core on a real Alchitry board with a scope and serial soaks: the 25 MHz clock, timing and what the simulators got right.
Switching on the soft core on a real FPGA board after twelve posts of simulation: dark LEDs, a silent serial port, and what the simulators missed.
A 24 LED Larson scanner in C with a fading tail, driven by a timer interrupt and two small PWM peripherals so the CPU can sleep.
Where the RISC-V soft core breaks: the bugs found, which tool caught each one, the limits of the design, and the biggest edge, that it had not met a board.
With no M extension, a multiply is a library loop. Timing mul, div and rem from inside the program using mtime on an RV32E soft core.
The first compiled C program on the RISC-V soft core: the rv32e cross compiler, a linker script, a start-up file and what it took to run hello.c.
Implementing WFI so the RISC-V soft core really stops its clock until an interrupt, and measuring the CPU about 89 percent asleep in simulation.
Why a divided CPU clock cannot do real time, and how moving the soft core onto one board clock with clock enables fixed it.
Adding mtime and mtimecmp, a timer interrupt and buttons to the soft core, climbing a timing ladder, and tracking down the button press that got lost.
Making an illegal instruction trap instead of becoming a nop: CSRs, mepc and mcause, MRET, and where the Zicsr extension fits in a RISC-V core.