Ampsand

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Amps <- & -> Embedded

  1. RISC-V soft core 4: Talking to the world

    RISC-V has no I/O instructions. Memory mapped I/O on the soft core: the address map, a UART, and a boot menu driven by loads and stores.

  2. RISC-V soft core 3: Harvard by accident, von Neumann by choice

    The RISC-V core was Harvard by accident. Moving to a single von Neumann memory, and the store that ran the old instruction word once.

  3. RISC-V soft core 2: Tests that can fail

    How to trust a CPU you wrote: tests you have seen fail, a single instruction encoder checked against the GNU assembler, and a RAM that was never there.

  4. RISC-V soft core 1: A CPU you can watch

    Building a tiny CPU from a program counter, memory, register file, ALU and control unit, until LEDs sweep along a row, and a double beat that was not a pipeline.

  5. RISC-V soft core 0: Firmware

    Why a firmware engineer went back to Mano's 1988 hardware design book and decided to build a RISC-V processor from scratch on an FPGA.