Simulator 4: The tick that was 25 times too fast

Mon, 19 Oct 2026 00:25:00 +1100

The tick that was 25 times too fast, and a simulator that found it by accident

Part 4 of the simulator thread. Previously: A second opinion. The other thread is the RISC-V soft core series.

By the time I had two simulators I thought I had the design well covered. The Alchitry simulator ran the Lucid, and Yosys ran the Verilog, and I had checked them against a model and against each other. Then I ran a third one, for fun, and it found something neither of them could.

Simulator 0: The simulator I use

Sun, 18 Oct 2026 17:00:00 +1100

The simulator I use, with the lid off

Part 0 of a second thread alongside the RISC-V soft core series. It runs in parallel: the CPU posts say what the machine does, these say how I watch it.

Series: RISC-V soft core and Simulator. Part 0 of the simulator thread, so no previous part. The first CPU post is A CPU you can watch.

The RISC-V posts show a lot of pictures of an FPGA board. None of them are the board yet. They are a simulator, and since I keep leaning on it I should say what it is, what is mine, and what is not.

Verilator on Ampsand

Simulator 4: The tick that was 25 times too fast

Simulator 0: The simulator I use