Verification on Ampsand

Simulator 4: The tick that was 25 times too fast

Mon, 19 Oct 2026 00:25:00 +1100

The tick that was 25 times too fast, and a simulator that found it by accident

Part 4 of the simulator thread. Previously: A second opinion. The other thread is the RISC-V soft core series.

By the time I had two simulators I thought I had the design well covered. The Alchitry simulator ran the Lucid, and Yosys ran the Verilog, and I had checked them against a model and against each other. Then I ran a third one, for fun, and it found something neither of them could.

Simulator 3: A second opinion

Sun, 18 Oct 2026 22:00:00 +1100

A second opinion, and a mutation that failed for the wrong reason

Part 3 of the simulator thread. Previously: A simulator that lies. The other thread is the RISC-V soft core series.

If the main simulator is a sample and not a verdict, I need a second one. Not a copy of the first, which would share its faults, but a simulator that gets things wrong in different places, or not at all.

Simulator 2: A simulator that lies

Sun, 18 Oct 2026 21:00:00 +1100

A simulator that lies, and a mutation that should not have failed

Part 2 of the simulator thread. Previously: Why the IDE simulates at 284 Hz. The other thread is the RISC-V soft core series.

In part 2 of the CPU series I said to break your design on purpose and watch the right test fail. This is the story of a break where the test failed and my reasoning said it should not have.

RISC-V soft core 2: Tests that can fail

Sun, 18 Oct 2026 18:00:00 +1100

Tests that can fail, and a RAM that was never there

Part 2 of the RISC-V soft core series. Previously: A CPU you can watch.

A light that sweeps along a row of LEDs is a nice demo and a poor proof. It tells me that a handful of instructions work in one order. It says nothing about all the others, or about the edges of the ones I used. If this core is going to run real code I need to be able to trust it, and I need to know how much I can trust it.