https://dean.sellers.id.au/tags/timers/ Recent content in Timers on Ampsand Hugo en-AU Dean Sellers Thu, 29 Oct 2026 12:04:08 +1100 https://dean.sellers.id.au/2026/10/19/riscv-06-time-and-interrupts/ Mon, 19 Oct 2026 00:15:00 +1100 https://dean.sellers.id.au/2026/10/19/riscv-06-time-and-interrupts/ <p class="post-subtitle">Time and interrupts: a timer, some buttons, and the press that got lost</p><p><em>Part 6 of the RISC-V soft core series. Previously: <a href="https://dean.sellers.id.au/2026/10/19/riscv-05-when-it-goes-wrong/">When it goes wrong on purpose</a>.</em></p> <p>A trap is the program&rsquo;s own fault. An <strong>interrupt</strong> is the outside world getting the processor&rsquo;s attention, and the outside world does not wait for a convenient moment. It is the same mechanism with a different cause: the core stops what it is doing, remembers where it was, runs a handler, and goes back.</p>