https://dean.sellers.id.au/tags/time-domains/ Recent content in Time-Domains on Ampsand Hugo en-AU Dean Sellers Thu, 29 Oct 2026 12:04:08 +1100 https://dean.sellers.id.au/2026/10/19/riscv-07-one-clock/ Mon, 19 Oct 2026 00:20:00 +1100 https://dean.sellers.id.au/2026/10/19/riscv-07-one-clock/ <p class="post-subtitle">One clock, and why slow mode cannot do real time</p><p><em>Part 7 of the RISC-V soft core series. Previously: <a href="https://dean.sellers.id.au/2026/10/19/riscv-06-time-and-interrupts/">Time and interrupts</a>.</em></p> <p>For most of this project the core had two clocks. There was the board&rsquo;s fast oscillator, which ran the UART, the display and the debouncers, and there was the <em>CPU clock</em>, which the front panel made by dividing the fast one and which it could stop, start and single step.</p>