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		<title>Testing on Ampsand</title>
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		<description>Recent content in Testing on Ampsand</description>
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			<copyright>Dean Sellers</copyright>
		
		
			<lastBuildDate>Thu, 29 Oct 2026 12:04:08 +1100</lastBuildDate>
		
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				<title>RISC-V soft core 2: Tests that can fail</title>
				<link>https://dean.sellers.id.au/2026/10/18/riscv-02-tests-that-can-fail/</link>
				<pubDate>Sun, 18 Oct 2026 18:00:00 +1100</pubDate>
				<guid>https://dean.sellers.id.au/2026/10/18/riscv-02-tests-that-can-fail/</guid>
				<description>&lt;p class=&#34;post-subtitle&#34;&gt;Tests that can fail, and a RAM that was never there&lt;/p&gt;&lt;p&gt;&lt;em&gt;Part 2 of the RISC-V soft core series. Previously: &lt;a href=&#34;https://dean.sellers.id.au/2026/10/18/riscv-01-a-cpu-you-can-watch/&#34;&gt;A CPU you can watch&lt;/a&gt;.&lt;/em&gt;&lt;/p&gt;&#xA;&lt;p&gt;A light that sweeps along a row of LEDs is a nice demo and a poor proof. It tells me that a handful of instructions work in one order. It says nothing about all the others, or about the edges of the ones I used. If this core is going to run real code I need to be able to trust it, and I need to know &lt;em&gt;how much&lt;/em&gt; I can trust it.&lt;/p&gt;</description>
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