Amps <- & -> Embedded
A scrolling text demo ran too fast in simulation, which led to a timer divider that was 25 times too small and a third simulator that found it by accident.
Using Yosys as a second simulator, independent of the Alchitry one because it reads generated Verilog, and a mutation that failed for the wrong reason.
A mutation test that failed when my reasoning said it should pass, and the simulator that reported loads writing nothing to the register file.
Why the Alchitry IDE simulated the design at 284 Hz instead of 1 kHz, the first guess that was wrong, and the wrong place I was looking.
The Verilator based simulator behind the RISC-V posts: why not the one built into Alchitry Labs, what it is, what is mine, and what is not.