Riscv-Cpu-Sim on Ampsand

Simulator 4: The tick that was 25 times too fast

Mon, 19 Oct 2026 00:25:00 +1100

The tick that was 25 times too fast, and a simulator that found it by accident

Part 4 of the simulator thread. Previously: A second opinion. The other thread is the RISC-V soft core series.

By the time I had two simulators I thought I had the design well covered. The Alchitry simulator ran the Lucid, and Yosys ran the Verilog, and I had checked them against a model and against each other. Then I ran a third one, for fun, and it found something neither of them could.

Simulator 3: A second opinion

Sun, 18 Oct 2026 22:00:00 +1100

A second opinion, and a mutation that failed for the wrong reason

Part 3 of the simulator thread. Previously: A simulator that lies. The other thread is the RISC-V soft core series.

If the main simulator is a sample and not a verdict, I need a second one. Not a copy of the first, which would share its faults, but a simulator that gets things wrong in different places, or not at all.

Simulator 2: A simulator that lies

Sun, 18 Oct 2026 21:00:00 +1100

A simulator that lies, and a mutation that should not have failed

Part 2 of the simulator thread. Previously: Why the IDE simulates at 284 Hz. The other thread is the RISC-V soft core series.

In part 2 of the CPU series I said to break your design on purpose and watch the right test fail. This is the story of a break where the test failed and my reasoning said it should not have.

Simulator 1: Why the IDE simulates at 284 Hz

Sun, 18 Oct 2026 20:00:00 +1100

284 clocks a second, and the wrong place to look

Part 1 of the simulator thread. Previously: The simulator I use. The other thread is the RISC-V soft core series.

The IDE’s board view has a little readout in the corner. It said Running at 284 Hz, in red, because it wanted 1 kHz and could not get there. The board’s clock was 100 MHz, so the simulator was running the design more than three hundred thousand times slower than the real thing, and the Larson scanner crawled across the LEDs.

Simulator 0: The simulator I use

Sun, 18 Oct 2026 17:00:00 +1100

The simulator I use, with the lid off

Part 0 of a second thread alongside the RISC-V soft core series. It runs in parallel: the CPU posts say what the machine does, these say how I watch it.

Series: RISC-V soft core and Simulator. Part 0 of the simulator thread, so no previous part. The first CPU post is A CPU you can watch.

The RISC-V posts show a lot of pictures of an FPGA board. None of them are the board yet. They are a simulator, and since I keep leaning on it I should say what it is, what is mine, and what is not.