Performance on Ampsand

RISC-V soft core 10: What does a multiply cost?

Mon, 19 Oct 2026 00:40:00 +1100

What does a multiply cost?

Part 10 of the RISC-V soft core series. Previously: First C on the core.

The first C program had a line in it that looks harmless: a * b. On a modern laptop that is one instruction and a few clock cycles. On this core there is no instruction for it. The core is RV32E with no M extension, so no mul, no div and no rem. The compiler turns each *, / and % into a call to a library routine, a loop of shifts and adds that runs as ordinary code.

Simulator 1: Why the IDE simulates at 284 Hz

Sun, 18 Oct 2026 20:00:00 +1100

284 clocks a second, and the wrong place to look

Part 1 of the simulator thread. Previously: The simulator I use. The other thread is the RISC-V soft core series.

The IDE’s board view has a little readout in the corner. It said Running at 284 Hz, in red, because it wanted 1 kHz and could not get there. The board’s clock was 100 MHz, so the simulator was running the design more than three hundred thousand times slower than the real thing, and the Larson scanner crawled across the LEDs.