RISC-V soft core 3: Harvard by accident, von Neumann by choice

Sun, 18 Oct 2026 19:00:00 +1100

Harvard by accident, von Neumann by choice, and a store that runs the old word once

Part 3 of the RISC-V soft core series. Previously: Tests that can fail.

I was reading the memory map when I asked a question that sounds too simple to matter: so the map contains no ROM?

It did not. The map described the data side of the core, a block of RAM and a UART. The program lived somewhere else entirely, in a ROM on its own bus, addressed by the program counter. Loads and stores could not reach it. Instruction address 0 was a different place from data address 0.

Memory on Ampsand

RISC-V soft core 3: Harvard by accident, von Neumann by choice