Amps <- & -> Embedded
Making an illegal instruction trap instead of becoming a nop: CSRs, mepc and mcause, MRET, and where the Zicsr extension fits in a RISC-V core.
RISC-V has no I/O instructions. Memory mapped I/O on the soft core: the address map, a UART, and a boot menu driven by loads and stores.
Using Yosys as a second simulator, independent of the Alchitry one because it reads generated Verilog, and a mutation that failed for the wrong reason.
A mutation test that failed when my reasoning said it should pass, and the simulator that reported loads writing nothing to the register file.
Why the Alchitry IDE simulated the design at 284 Hz instead of 1 kHz, the first guess that was wrong, and the wrong place I was looking.
The RISC-V core was Harvard by accident. Moving to a single von Neumann memory, and the store that ran the old instruction word once.
How to trust a CPU you wrote: tests you have seen fail, a single instruction encoder checked against the GNU assembler, and a RAM that was never there.
The Verilator based simulator behind the RISC-V posts: why not the one built into Alchitry Labs, what it is, what is mine, and what is not.
Building a tiny CPU from a program counter, memory, register file, ALU and control unit, until LEDs sweep along a row, and a double beat that was not a pipeline.
Why a firmware engineer went back to Mano's 1988 hardware design book and decided to build a RISC-V processor from scratch on an FPGA.