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		<title>Exceptions on Ampsand</title>
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		<description>Recent content in Exceptions on Ampsand</description>
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			<copyright>Dean Sellers</copyright>
		
		
			<lastBuildDate>Thu, 29 Oct 2026 12:04:08 +1100</lastBuildDate>
		
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				<title>RISC-V soft core 5: When it goes wrong on purpose</title>
				<link>https://dean.sellers.id.au/2026/10/19/riscv-05-when-it-goes-wrong/</link>
				<pubDate>Mon, 19 Oct 2026 00:10:00 +1100</pubDate>
				<guid>https://dean.sellers.id.au/2026/10/19/riscv-05-when-it-goes-wrong/</guid>
				<description>&lt;p class=&#34;post-subtitle&#34;&gt;When it goes wrong on purpose: traps&lt;/p&gt;&lt;p&gt;&lt;em&gt;Part 5 of the RISC-V soft core series. Previously: &lt;a href=&#34;https://dean.sellers.id.au/2026/10/19/riscv-04-talking-to-the-world/&#34;&gt;Talking to the world&lt;/a&gt;.&lt;/em&gt;&lt;/p&gt;&#xA;&lt;p&gt;Up to now, if the core was handed an instruction it did not understand, it treated it as a &lt;code&gt;nop&lt;/code&gt; and carried on. That is the worst possible answer. A program that goes wrong should &lt;em&gt;stop and say so&lt;/em&gt;, and the rest of the machine should be able to decide what to do about it.&lt;/p&gt;</description>
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